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1 buck pwm controller with internal compensation and external reference tracking ISL95873 the ISL95873 is a single-phase synchronous-buck pwm controller featuring intersil?s proprietary r4? technology. the r4? modulator has integrated compensation, fast transient performance, accurate switching frequency control, and excellent light-load efficiency . these technology advances, together with integrated mosfet drivers and a schottky bootstrap diode, allow for a high performance regulator that is highly compact and needs few external components. differential remote sensing of the output voltage is an additional feature. for maximum efficiency, the converter automatically enters diode-emulation mode (dem) during light-load conditions, such as system standby. the ISL95873 accepts a wide 3.3v to 25v input voltage range, making it ideal for systems that run on battery or ac-adapter power sources. it also is a low- cost solution for applications requiring tracking of an exte rnal reference voltage during soft-start. when the external reference level meets the internal reference voltage, the ISL95873 switches from the external reference to the internal reference. the external reference is only used during soft-start. features ? external reference tracking ? intersil?s r4? modulator technology - internal compensation - fast, optimal transient response ? input voltage range: 3.3v to 25v ? output voltage range: 0.5v to 3.3v ? precision voltage regulation - 0.5% system accuracy over -10c to +100c ?output voltage remote sense ? fixed 300khz pwm frequency in continuous conduction - proprietary frequency control loop ? automatic diode emulation mode for highest efficiency ? power-good monitor for soft-start and fault detection applications ? compact buck regulators requiring external tracking figure 1. ISL95873 application schematic with dcr current sense rtn gnd refin en c boot l o c sen r ocset q hs q ls 3.3v to 25v 0.5v to 3.3v r o co cin v in v out c soft c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo ocset fb sref vcc pvcc lgate pgnd 11 ugate boot 2 1 12 9 pgood phase 4 3 10 +5v r vcc r pgood rtn1 r fb r ofs r ofs1 r fb1 rtn1 0 external reference voltage december 10, 2012 fn8390.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved. r3 , r4 modulator technologies and intersil (and design) are trad emarks owned by intersil corporation or one of its subsidiarie s. all other trademarks mentioned are the property of their respective owners.
ISL95873 2 fn8390.0 december 10, 2012 application schematics figure 2. ISL95873 application schematic with one output voltage setpoint and dcr current sense figure 3. ISL95873 application schematic with one ou tput voltage setpoint and resistor current sense rtn gnd refin en c boot l o c sen r ocset q hs q ls 3.3v to 25v 0.5v to 3.3v r o co cin v in v out c soft c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo ocset fb sref vcc pvcc lgate pgnd 11 ugate boot 2 112 9 pgood phase 4 310 +5v r vcc r pgood rtn1 r fb r ofs r ofs1 r fb1 rtn1 0 external reference voltage rtn gnd refin en c boot l o c sen r ocset q hs q ls 3.3v to 25v 0.5v to 3.3v r o co cin v in v out c soft c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo ocset fb vcc pvcc lgate pgnd 11 ugate boot 2 112 9 pgood phase 4 310 +5v r vcc r pgood rtn1 r fb r 2 r sen r ofs1 r fb1 rtn1 0 external reference voltage sref r 1 r ofs
ISL95873 3 fn8390.0 december 10, 2012 block diagram figure 4. simplified functional block diagram of ISL95873 driver driver boot ugate phase pvcc lgate pgnd overcurrent undervoltage soft-start circuitry r4 tm modulator dead-time generation pgood circuitry reference voltage circuitry por vo ocset fb pgood sref vcc rtn en internal compensation amplifier + gnd remote sense circuitry refin monitor
ISL95873 4 fn8390.0 december 10, 2012 ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL95873hruz-t 873 -10 to +100 16 ld 2.6x1.8 utqfn l16.2.6x1.8a notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate-e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL95873 . for more information on msl, please see tech brief tb363 pin configuration ISL95873 (16 ld 2.6x1.8 utqfn) top view functional pin descriptions pin number symbol description 1 gnd ic ground for bias supply and signal reference. 2 rtn negative remote sense input of v out . if resistor divider consisting of r fb and r ofs is used at fb pin, the same resistor divider should be used at rtn pin, i.e. keep r fb1 = r fb , and r ofs1 = r ofs . 3 en enable input for the ic. pulling en above the rising threshold voltage initializes the soft-start sequence. 4 refin input for supplying the external reference voltage followed by the controller during soft-start. 5 sref soft-start and voltage slew-rate programming capacitor input. connects in ternally to the inverting input of the v set voltage setpoint amplifier. 6 fb voltage feedback sense input. connects internally to the inverting input of the control-loop error amplifier. the converter is in regulation when the voltage at the fb pin equals the voltage on the sref pin. 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 gnd rtn en refin boot ugate phase pgood pgnd lgate pvcc vcc sref fb ocset vo 7 ocset input for the overcurrent detection circuit. the overcurrent setpoint programming resistor r ocset connects from this pin to the sense node. 8 vo output voltage sense input for the r4 tm modulator. the vo pin also serves as the reference input for the overcurrent detection circuit. 9 pgood power-good open-drain indicator output. this pin changes to high impedance when the converter is able to supply regulated voltage. 10 phase return current path for the ugate high-side mosfet driver, v in sense input for the r4 tm modulator, and inductor current polarity detector input. 11 ugate high-side mosfet gate driver output. connect to the gate terminal of the high-side mosfet of the converter. 12 boot positive input supply for the ugate high-side mosfet gate driver. the boot pin is internally connected to the cathode of the schottky boot-strap diode. connect an mlcc between the boot pin and the phase pin. 13 vcc input for the ic bias voltage. connect +5v to the vcc pin and decouple with at least a mlcc to the gnd pin. 14 pvcc input for the lgate and ugate mosfet driver circuits. the pvcc pin is internally connected to the anode of the schottky boot-strap diode. connect +5v to the pvcc pin and decouple with a mlcc to the pgnd pin. 15 lgate low-side mosfet gate driver output. connect to the gate terminal of the low-side mosfet of the converter. 16 pgnd return current path for the lgate mosfet driver. connect to the source of the low-side mosfet. functional pin descriptions (continued) pin number symbol description
ISL95873 5 fn8390.0 december 10, 2012 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 enabling the controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 external reference setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 r4tm modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pgood monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 integrated mosfet gate-drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 adaptive shoot-through protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 general application design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 selecting the lc output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 selecting the input capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 selecting the bootstrap capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 driver power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 mosfet selection and considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 package outline drawing l16.2.6x1.8a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ISL95873 6 fn8390.0 december 10, 2012 absolute maximum rating s thermal information vcc, pvcc, pgood, fsel to gnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v vcc, pvcc to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v gnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v en, vo, refin, fb, rtn, ocset, sref . . . . . . . . . -0.3v to gnd, vcc + 0.3v boot voltage (v boot-gnd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 33v boot to phase voltage (v boot-phase ). . . . . . . . . . . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) phase voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 28v gnd -8v (<20ns pulse width, 10j) ugate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot v phase - 5v (<20ns pulse width, 10j) to v boot lgate voltage . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v (dc) to vcc + 0.3v . . . . . . . . . . . . . . . . . . gnd - 2.5v (<20ns pulse width, 5j) to vcc + 0.3v thermal resistance (typical) ja (c/w) jc (c/w) 16 ld utqfn (notes 4, 5) . . . . . . . . . . . . . . 90 60 junction temperature range . . . . . . . . . . . . . . . . . . . . . . . -55 c to +150 c operating temperature range . . . . . . . . . . . . . . . . . . . . . .-10c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c converter input voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . 3.3v to 25v vcc, pvcc to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications all typical specifications t a = +25c, v cc = 5v. boldface limits apply over the operating temperature range, -10c to +100c, unless otherwise stated. parameter symbol test conditions min (note 7) typ max (note 7) unit vcc and pvcc vcc input bias current i vcc en = 5v, vcc = 5v, fb = 0.55v, sref < fb - 1.2 1.9 ma vcc shutdown current i vccoff en = gnd, vcc = 5v - 0 1.0 a pvcc shutdown current i pvccoff en = gnd, pvcc = 5v - 0 1.0 a vcc por threshold rising vcc por threshold voltage v vcc_thr 4.40 4.52 4.60 v falling vcc por threshold voltage v vcc_thf 4.10 4.22 4.35 v regulation system accuracy pwm mode = ccm -0.5 - +0.5 % internal reference voltage - 0.5 - v feedback voltage reference transfer voltage 0.461 0.482 0.4975 v pwm switching frequency accuracy f sw pwm mode = ccm 255 300 345 khz vo vo input impedance r vo en = 5v - 600 - k vo reference offset current i voss v enthr < en, sref = soft-start mode - 8.5 - a vo input leakage current i vooff en = gnd, vo = 3.6v - 0 - a error amplifier fb input bias current i fb en = 5v, fb = 0.50v -30 - +50 na sref maximum soft-start current i ss sref = soft-start mode 51 85 119 a power good pgood pull-down impedance r pg pgood = 5ma sink - 50 150
ISL95873 7 fn8390.0 december 10, 2012 pgood leakage current i pg pgood = 5v - 0.1 1.0 a gate driver ugate pull-up resistance (note 6) r ugpu 200ma source current - 1.1 1.7 ugate source current (note 6) i ugsrc ugate - phase = 2.5v - 1.8 - a ugate sink resistance (note 6) r ugpd 250ma sink current - 1.1 1.7 ugate sink current (note 6) i ugsnk ugate - phase = 2.5v - 1.8 - a lgate pull-up resistance (note 6) r lgpu 250ma source current - 1.1 1.7 lgate source current (note 6) i lgsrc lgate - gnd = 2.5v - 1.8 - a lgate sink resistance (note 6) r lgpd 250ma sink current - 0.55 1.0 lgate sink current (note 6) i lgsnk lgate - pgnd = 2.5v - 3.6 - a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load - 21 - ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load - 21 - ns phase phase input impedance r phase - 33 - k bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma - 0.58 - v reverse leakage i r v r = 25v - 0 - a control inputs en high threshold voltage v enthr 2.0 - - v en low threshold voltage v enthf - - 1.0 v en input bias current i en en = 5v 0.85 1.7 2.55 a en leakage current i enoff en = gnd - 0 1.0 a protection ocp threshold voltage v ocpth v ocset - v o -1.15 - 1.15 mv ocp reference current i ocp en = 5.0v 7.905 8.5 8.925 a ocset input resistance r ocset en = 5.0v - 600 - k ocset leakage current i ocset en = gnd - 0 - a uvp threshold voltage v uvth v fb = %v sref 81 84 87 % ovp rising threshold voltage v ovrth v fb = %v sref 113 116 120 % ovp falling threshold voltage v ovfth v fb = %v sref 100 102 106 % otp rising threshold temperature (note 6) t otrth - 150 - c otp hysteresis (note 6) t othys - 25 - c notes: 6. limits established by characteriza tion and are not production tested. 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications all typical specifications t a = +25c, v cc = 5v. boldface limits apply over the operating temperature range, -10c to +100c, unless otherwise stated. (continued) parameter symbol test conditions min (note 7) typ max (note 7) unit
ISL95873 8 fn8390.0 december 10, 2012 theory of operation the following sections will provide a detailed description of the inner workings of the ISL95873. power-on reset the ic is disabled until the voltage at the vcc pin has increased above the rising power-on reset (por) threshold voltage v vcc_thr . the controller will become disabled when the voltage at the vcc pin decreases below the falling por threshold voltage v vcc_thf . the por detector has a noise filter of approximately 1s. enabling the controller once vcc has ramped above v vcc_thr , the controller can be enabled by pulling the en pin voltage above the input-high threshold v enthr . once en exceeds this threshold, the soft-start sequence is initiated. external reference setup the refin input of the ISL95873 requires an external reference voltage to be connected to this pin. typically, this will be another system rail, which requires the output of the ISL95873 to follow it up during boot-up of the two regulators. a resistor divider is required between the external reference voltage and the refin pin to scale the external voltage down to the internal reference voltage, see figure 5. the relation between the voltage at the refin pin, v refin , and the external reference voltage, v ext , is given in equation 1: from this expression the resi stor divider values can be calculated. the voltage on the refin pin must equal to the internal reference of the ISL95873. soft-start once the por threshold on vcc has been met and enable is applied, the sref pin releases its discharge clamp, and enables the reference amplifier v set . the soft-start current i ss is limited to 85a and is sourced out of th e sref pin and begins charging the c soft capacitor on the sref pin until it equals v refin . the soft-start current will adjust to match the external reference ramp rate as seen through the resistor divider on the refin pin. the regulator controls the pwm, such that the voltage on the sref pin tracks the rising voltage on the refin pin. the maximum dv/dt that the external voltage (v ext ) can achieve is outlined in equation 2. the elapsed time from when the en pin is asserted to when v sref has charged c soft to v ref in will depend on the dv/dt of the external reference voltage used to generate the signal at refin. c soft will not impact the dv/dt unless it is over sized or the dv/dt (outlined in equation 2), is exceeded by the external reference. the minimum c soft capacitance is 10nf. once the feedback voltage, fb, exceeds the 0.482v threshold on an internal comparator, the isl9 5873 switches from the external reference (v ext ) to the internal reference, v ref , see figure 6. the end of soft-start is detected by i ss tapering off when capacitor c soft charges to v refin . the pull-down on pgood is released to indicate that the controller is regulating properly. during soft-start, the regulator always operates in ccm until the soft-start sequence is complete. once soft-start is complete, diode emulation mode (dem) is enabled. if refin is pre-charged, the ISL95873 will begin switching and charging the output voltage of the regulator to the pre-charged refin level once enabled. then the controller waits for refin to begin to move and starts charging the sref capacitor and ramping as described previously. output voltage programming the ISL95873 has a fixed 0.5v internal reference voltage (v sref ). figure 7 shows that the output voltage is the reference voltage if r fb is shorted and r ofs is open. a resistor divider consisting of r ofs and r fb allows the user to scale the output voltage between 0.5v and 3.3v. the relation between the output voltage and the reference voltage is given in equation 3: figure 5. refin connection to system rail refin v set + - v ref c soft ea + - fb r ofs r fb v out v comp v refin - + 0.482v sref r 1 r 2 v ext fb v refin v ref v ext r 2 r 1 r 2 + -------------------- - ? == (eq. 1) dv ext dt ------------------ - i ss c soft ------------------- r 1 r 2 + r 2 -------------------- - ? = (eq. 2) figure 6. soft-start tracking of external reference v ext v refin v ref slope determined by load current v out v ref r fb r ofs + r ofs --------------------------------- - ? = (eq. 3)
ISL95873 9 fn8390.0 december 10, 2012 r4 tm modulator the r4? modulator is an evolutionary step in r3? technology. like r3?, the r4? modulator allows variable frequency in response to load transients and maintains the benefits of current-mode hysteretic controllers. however, in addition, the r4? modulator reduces regulator output impedance and uses accurate referencing to eliminate the need for a high-gain voltage amplifier in the compensation loop. the result is a topology that can be tuned to voltage-mode hysteretic transient speed while maintaining a linear control model and removes the need for any compensation. this greatly simplifies the regulator design for customers and reduces external component cost. stability the removal of compensation derives from the r4? modulator?s lack of need for high dc gain. in traditional architectures, high dc gain is achieved with an integrator in the voltage loop. the integrator introduces a pole in the open-loop transfer function at low frequencies. thus, combined with the double-pole from the output l/c filter, creates a thr ee pole system that must be compensated to ma intain stability. classic control theory requires a single-pole transition through unity gain to ensure a stable sy stem. current-mode architectures (includes peak, peak-valley, current-mode hysteretic, r3? and r4?) generate a zero at or near the l/c resonant point, effectively canceling one of the system?s poles. the system still contains two poles, one of which must be canceled with a zero before unity gain crossover to achieve stability. compensation components are added to introduce the necessary zero. figure 8 illustrates the classic integrator configuration for a voltage loop error-amplifier. while the integrator provides the high dc gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loop. figure 9 shows the open-loop response that results from the addition of an integrating capacitor in the voltage loop. the compensation components found in figure 8 are necessary to achieve stability. because r4? does not require a high-gain voltage loop, the integrator can be removed, redu cing the number of inherent poles in the loop to two. the current-mode zero continues to cancel one of the poles, ensuri ng a single-pole crossover for a wide range of output filter choice s. the result is a stable system with no need for compensation components or complex equations to properly tune the stability. figure 10 shows the r4? error-amplifier that does not require an integrator for high dc gain to achieve accurate regulation. the result to the open loop respon se can be seen in figure 11. figure 7. ISL95873 voltage programming circuit sref v set + - v ref c soft ea + - fb r ofs r fb v out v comp figure 8. integrator error-amplifier configuration v integrator for high dc gain compensation to counter integrator pole v out v dac v comp figure 9. uncompensated integrator open-loop response f (hz) p1 p2 p3 l/c double-pole integrator pole z1 zero - 6 0 d b / d e c - 20 d b /dec -20db crossover required for stability compensator to add z2 is needed - 4 0 d b / d e c r3 tm loop gain (db) current-mode
ISL95873 10 fn8390.0 december 10, 2012 transient response in addition to requiring a compen sation zero, the integrator in traditional architectures also slow s system response to transient conditions. the change in comp vo ltage is slow in response to a rapid change in output voltage. if the integrating capacitor is removed, comp moves as quickly as v out , and the modulator immediately increase s or decreases switching frequency to recover the output voltage. the dotted red and blue lines in figure 12 represent the time delayed behavior of v out and v comp in response to a load transient when an integrator is used. the solid red and blue lines illustrate the increased response of r4? in the absence of the integrator capacitor. diode emulation the polarity of the output inductor current is defined as positive when conducting away from the phase node, and defined as negative when conducting towards the phase node. the dc component of the inductor current is positive, but the ac component known as the ripple curren t, can be either positive or negative. should the sum of the ac and dc components of the inductor current remain positive for the entire switching period, the converter is in continuous-conduction-mode (ccm). however, if the inductor current becomes negative or zero, the converter is in discontinuous-conduction-mode (dcm). unlike the standard dc/dc buck regulator, the synchronous rectifier can sink current from the output filter inductor during dcm, reducing the light-load efficiency with unnecessary conduction loss as the low-side mosfet sinks the inductor current. the ISL95873 controller avoids the dcm conduction loss by making the low-side mosfet emulate the current-blocking behavior of a diode. this smart-diode operation called diode-emulation-mode (dem) is triggered when the negative inductor current produces a positive voltage drop across the r ds(on) of the low-side mosfet for eight consecutive pwm cycles while the lgate pin is high. the converter will exit dem on the next pwm pulse after detecting a negative voltage across the r ds(on) of the low-side mosfet. it is characteristic of the r4? architecture for the pwm switching frequency to decrease while in dcm, increasing efficiency by reducing unnecessary gate-driver switching losses. the extent of the frequency reduction is proporti onal to the reduction of load current. upon entering dem, the pwm frequency is forced to fall approximately 30% by forcing a si milar increase of the window voltage v w . this measure is taken to prevent oscillating between modes at the boundary between ccm and dcm. the 30% increase of v w is removed upon exit of dem, forcing the pwm switching frequency to jump back to the nominal ccm value. overcurrent the overcurrent protection (ocp) setpoint is programmed with resistor r ocset , which is connected across the ocset and phase pins. resistor r o is connected between the vo pin and the actual output voltage of the converter. during normal operation, the vo pin is a high impedance path, therefore there is no voltage drop across r o . the value of resistor r o should always match the value of resistor r ocset . figure 10. non-integrated r4 tm error-amplifier configuration v out v dac r 1 r 2 v comp figure 11. uncompensated r4 tm open-loop response f (hz) p1 p2 l/c double-pole z1 current-mode zero -20db /d e c system has 2 poles and 1 zero no compensator is needed r4 tm loop gain (db) -20db/dec - 4 0 d b / d e c figure 12. r3 tm vs r4 tm idealized transient response r3 tm i t v comp r4 tm t t i out t t t v out
ISL95873 11 fn8390.0 december 10, 2012 figure 13 shows the overcurrent set circuit. the inductor consists of inductance l and the dc resistance dcr. the inductor dc current i l creates a voltage drop across dcr, which is given by equation 4: the i ocset current source sinks 8.5a into the ocset pin, creating a dc voltage dr op across the resistor r ocset , which is given by equation 5: the dc voltage difference between the ocset pin and the vo pin, given by equation 6: the ic monitors the voltage of the ocset pin and the vo pin. when the voltage of the ocset pin is higher than the voltage of the vo pin for more than 10s, an ocp fault latches the converter off. the value of r ocset is calculated with equation 7, which is written as: where: -r ocset ( ) is the resistor used to program the overcurrent setpoint -i oc is the output dc load current that will activate the ocp fault detection circuit - dcr is the inductor dc resistance for example, if i oc is 20a and dcr is 4.5m , the choice of r ocset is equal to 20a x 4.5m /8.5a = 10.5k . resistor r ocset and capacitor c sen form an r-c network to sense the inductor current. to sense the inductor current correctly not only in dc operation, but also during dynamic operation, the r-c network time constant r ocset c sen needs to match the inductor time constant l/dcr. the value of c sen is then written as equation 8: for example, if l is 1.5h, dcr is 4.5m , and r ocset is 9k , the choice of c sen = 1.5h/(9k x 4.5m ) = 0.037f . when an ocp fault is declared, the converter will be latched off and the pgood pin will be asserted low. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . overvoltage the overvoltage (ov) detection ci rcuit triggers after the fb pin voltage is above the rising overvoltage threshold v ovrth for more than 2s. for example, if the converter is programmed to regulate 1.0v at the fb pin, that voltage wo uld have to rise above the typical v ovrth threshold of 116% for more than 2s to trigger an ov. in numerical terms, that would be 116% x 1.0v = 1.16v. when an ov is detected, the converter will take pgood low and continue to switching. the converter is not latched off. when the converter output voltage drops below the falling overvoltage threshold, v ovfth , for more than 2s then pgood is taken high again and the ov detection is considered cleared. the falling overvoltage threshold v ovfth is typically 102%. that means if the fb pin voltage falls below 102% x 1.0v = 1.02v for more than 2s, the controller will return pgood high. figure 14 shows a simple illustration of pgood operation during an ov detection event. the cross hatch portion of the pgood waveform shown represents the 2s recognition time prior to the pgood transition. undervoltage the uvp fault detection circuit triggers after the fb pin voltage is below the undervoltage threshold v uvth for more than 2s. for example, if the converter is progra mmed to regulate 1.0v at the fb pin, that voltage would have to fall below the typical v uvth threshold of 84% for more than 2s in order to trip the uvp fault latch. in numerical terms, that would be 84% x 1.0v = 0.84v. when a uvp fault is declared, the converter will be latched off and the pgood pin will be asserted lo w. the fault will remain latched until the en pin has been pulle d below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . figure 13. overcurrent programming circuit phase c o l v o r ocset c sen ocset vo r o dcr i l 8.5a + _ v dcr + _ v rocset v dcr i l dcr ? = (eq. 4) v rocset 8.5 ar ocset ? = (eq. 5) v ocset v ? vo v dcr v ? rocset i l dcr ? i ocset r ocset ? ? == (eq. 6) (eq. 7) r ocset i oc dcr ? i ocset ---------------------------- = (eq. 8) c sen l r ocset dcr ? ------------------------------------------ = figure 14. overvoltage operation enable ccm/dcm operation mosfet pgood vout 116% 102%
ISL95873 12 fn8390.0 december 10, 2012 over-temperature when the temperature of the ic increases above the rising threshold temperature t otrth , it will enter the otp state that suspends the pwm, forcing the lgate and ugate gate-driver outputs low. the status of the pgood pin does not change nor does the converter latch-off. the pwm remains suspended until the ic temperature falls below the hysteresis temperature t othys at which time normal pwm operation resumes. the otp stat e can be reset if the en pin is pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . all other protection circuits remain functional while the ic is in the otp state. it is likely that the ic will detect an uvp fault because in the absence of pwm, the output voltage decays below the undervoltage threshold v uvth . pgood monitor the pgood pin indicates when the converter is capable of supplying regulated voltage. the pgood pin is an undefined impedance if the vcc pin has not reached the rising por threshold v vcc_thr , or if the vcc pin is below the falling por threshold v vcc_thf . if there is a fault condition of output overcurrent or undervoltage, pgood is asserted low. the pgood pull-down impedance is 50 . the pgood pin will transition lo w when an ov condition is detected, but will return high wh en the ov condition is removed. integrated mosfet gate-drivers the lgate pin and ugate pins are mosfet driver outputs. the lgate pin drives the low-side mosfet of the converter while the ugate pin drives the high-side mosfet of the converter. the lgate driver is optimized for low duty-cycle applications where the low-side mosfet experi ences long conduction times. in this environment, the low-side mosfets require exceptionally low r ds(on) and tend to have large pa rasitic charges that conduct transient currents within the devi ces in response to high dv/dt switching present at the phase no de. the drain-gate charge in particular can conduct sufficient current through the driver pull-down resistance that the v gs(th) of the device can be exceeded and turned on. for this reason, the lgate driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the mosfets gate voltage below v gs(th) . adaptive shoot-through protection adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1v. the dead-time shown in figure 15 is extended by the additional period that the falling gate voltage remains above the 1v threshold. the high-side gate-driver output voltage is measured across the ugate and phase pins while the low-side gate-driver output volt age is measured across the lgate and pgnd pins. the power for the lgate gate-driver is sourced directly from the pvcc pin. the power for the ugate gate-driver is supplied by a boot-strap capacitor connected across the boot and phase pins. the capacitor is charged each time the phase node voltage falls a diode drop below pvcc such as when the low-side mosfet is turned on. general application design guide this design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase buck converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs that include schematics, bill of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck converter is a function of the input and the output voltage. this relationship is expressed in equation 9: the output inductor peak-to-peak ripple current is expressed in equation 10: a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon several crit eria, such as mosfet switching loss, inductor core loss, and the resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated using equation 11: where, i load is the converter output dc current. the copper loss can be significant so close attention needs to be given to the dcr of the inductor. another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. a saturated inductor could cause destruction of circuit components, as well as nuisance ocp faults. figure 15. gate drive adaptive shoot-through protection 1v 1v ugate lgate 1v 1v d v o v in --------- = (eq. 9) (eq. 10) i p-p v o 1d ? () ? f sw l ? ------------------------------ - = (eq. 11) p copper i load 2 dcr ? =
ISL95873 13 fn8390.0 december 10, 2012 a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are expressed in equations 12 and 13: if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of the capacitor can significantly impact the output voltage ripple and cause a brief volt age spike if the load transient has an extremely high slew rate. low inductance capacitors should be considered. a capacitor dissipa tes heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fa de as much as 50% as the dc voltage across it increases. selecting the input capacitor the important parameters for the bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current required by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. figure 16 is a graph of the input rms ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. the ripple current calculation is written as equation 14: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter duty cycle is written as equation 15: in addition to the bulk capacitors, some low esl ceramic capacitors are recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. selecting the bootstrap capacitor the integrated driver features an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor voltage rating is selected to be at least 10v. although the theoretical maximum voltage of the capacitor is pvcc-v diode (voltage drop across the boot diode), large excursions below ground by the phase node requires at least a 10v rating for the bootstrap capacitor. th e bootstrap capacitor can be chosen from equation 16: where: -q gate is the amount of gate charge required to fully charge the gate of the upper mosfet - v boot is the maximum decay across the boot capacitor as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs = 5v, and a v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a comfortable margin, select a capacitor that is double the calculated capacitance. in this example, 0.22f will suffice. use a low temperature-coefficient ceramic capacitor. driver power dissipation switching power dissipation in the driver is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the ma ximum recommended operating junction temperature of +125c. when designing the application, it is recommended th at the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the drivers is approximated as equation 17: v esr i p-p e ? sr = (eq. 12) v c i p-p 8c o f ? sw ? --------------------------------- = (eq. 13) figure 16. normalized input rms current for eff = 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 duty cycle normalized input rms ripple current x = 0.5 x = 0 x = 1 (eq. 14) i in_rms i max 2 dd 2 ? () ? () x 2 i max 2 d 12 ------ ?? ?? ?? + i max -------------------------------------------------------------------------------------------------------- = (eq. 15) d v o v in eff ? -------------------------- = c boot q gate v boot ----------------------- - (eq. 16) pf sw 1.5v u q u v l q l + () p l p u ++ = (eq. 17)
ISL95873 14 fn8390.0 december 10, 2012 where: -f sw is the switching frequency of the pwm signal -v u is the upper gate driver bias supply voltage -v l is the lower gate driver bias supply voltage -q u is the charge to be delivered by the upper driver into the gate of the mosfet and discrete capacitors -q l is the charge to be delivered by the lower driver into the gate of the mosfet and discrete capacitors -p l is the quiescent power consumption of the lower driver -p u is the quiescent power cons umption of the upper driver mosfet selection and considerations the choice of mosfets depends on the current each mosfet will be required to conduct, the swit ching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain-to-source voltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of th e upper voltage tolerance of the input power source and the voltage spike that occurs when the mosfets switch. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred high-side mosfet emphasizes low ga te charge so that the device spends the least amount of time dissipating power in the linear region. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. for the low-side mosfet, (ls), the power loss can be assumed to be conductive only and is written as equation 18: for the high-side mosfet, (hs), its conduction loss is written as equation 19: for the high-side mosfet, its switching loss is written as equation 20: where: -i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off layout considerations as a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board. the ground-plane layer should be adjacent to the signal layer to provide shielding. the ground plane layer should have an island located under the ic, the components connected to analog or logic signals. the island should be connected to th e rest of the ground plane layer at one quiet point. there are two sets of components in a dc/dc converter; the power components and the small signal components. the power components are the most critical because they switch large amount of energy. the small si gnal components connect to sensitive nodes or supply critic al bypassing current and signal coupling. the power components should be placed first and these include mosfets, input and output capacitors, and the inductor. keeping the distance between the power train and the control ic short helps keep the gate drive traces short. these drive signals include the lgate, ugate, pgnd, phase and boot. when placing mosfets, try to keep the source of the upper mosfets and the drain of the lower mosfets as close as thermally possible (see figure 18). input high frequency capacitors should be placed close to the drain of the upper mosfets and the source of the lower mosfets. place the output inductor and output capacitors between the mosfets and the load. high frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target, making use of the shortest connection paths to any internal planes. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. vcc and pvcc pins place the decoupling capacitors as close as practical to the ic. in particular, the pvcc decoupling capacitor should have a very short and wide connection to th e pgnd pin. the vcc decoupling capacitor should be referenced to gnd pin. en and pgood pins these are logic signals that are referenced to the gnd pin. treat as a typical logic signal. figure 17. power dissipation vs frequency frequency (hz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k power (mw) q u =50nc q l =50nc q u =20nc q l =50nc q u =50nc q l =100nc q u =100nc q l =200nc (eq. 18) p con_ls i load 2 r ? ds on () _ls 1d ? () ? p con_hs i load 2 r ? ds on () _hs d ? = (eq. 20) p sw_hs v in i valley t on f ? sw ?? 2 --------------------------------------------------------------------- - v in i peak t off f ? sw ?? 2 ----------------------------------------------------------------- - + =
ISL95873 15 fn8390.0 december 10, 2012 ocset and vo pins the current-sensing network consisting of r ocset , r o , and c sen needs to be connected to the inductor pads for accurate measurement of the dcr voltage drop. these components however, should be located physically close to the ocset and vo pins with traces leading back to th e inductor. it is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. the procedure is the same for resistive current sense. fb, sref, refin, and rtn pins the input impedance of these pins is high, making it critical to place the components connected to these pins as close as possible to the ic. lgate, pgnd, ugate, boot, and phase pins the signals going through these tr aces are high dv/dt and high di/dt, with high peak charging and discharging current. the pgnd pin can only flow current from the gate-source charge of the low-side mosfets when lgate goes low. ideally, route the trace from the lgate pin in parall el with the trace from the pgnd pin, route the trace from the ugate pin in parallel with the trace from the phase pin. in order to have more accurate zero-crossing detection of inductor current, it is recommended to connect the phase pin to the drain of the low-side mosfets with kelvin connection. these pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximity with these traces on any layer. inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets figure 18. typical power component placement vias to ground plane inductor high-side osfets input apacitors low-side osfets schottky iode output apacitors
ISL95873 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8390.0 december 10, 2012 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL95873 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change december 10, 2012 fn8390.0 initial release.
ISL95873 17 fn8390.0 december 10, 2012 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 k l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - k0.15 - - - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0- 12 4 rev. 5 2/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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